1. Field of the Invention
The present invention relates to a drive circuit for a display device, such as a liquid crystal device (LCD), which displays images by controlling pixels according to a digital video signal, and more particularly to a signal processing circuit in a drive circuit for supplying display data to a display device in which a digital video signal is allotted to multiple phases in the horizontal direction to perform display.
2. Description of Related Art
An active matrix LCD, being one example of a conventional display device, will be described. FIG. 1 is a block diagram of a conventional LCD and a drive circuit therefor. As shown in FIG. 1, a conventional LCD panel comprises a plurality of data lines 102 extending in the vertical direction, a plurality of gate lines 103 extending in the horizontal direction, a data line selector 104 for sequentially selecting one of the data lines 102, a gate driver 105 for sequentially selecting one of the gate lines 103 and applying a gate voltage to the selected gate line, a thin film transistor (TFT) 106 and a pixel electrode 107 disposed at each of intersections between the data lines 102 and the gate lines 103, a data supply line 108 for supplying display data output from a signal processing circuit 101 which processes an input video signal to the data lines 102, and TFTs 109 each having a gate connected to the data line selector 104.
An externally applied digital video signal is input to the driver 101 which, for example, temporarily stores and converts the input signal into an analog signal (DA conversion) before sequentially outputting display data (a pixel voltage) to be applied to the pixel electrode of each pixel. The gate driver 105 selects one of the gate lines 103 for every one horizontal scanning period to apply a gate voltage thereto, such that the TFTs 106 in the selected row are placed into an on-state. The data line selector 104 selects one of the plurality of TFTs 109 and turns one of the data lines 102 into an active state, to which a pixel voltage is applied. In this manner a pixel voltage is applied, through the TFT 106 disposed at an intersection of the selected data line 102 and the selected gate line 103, to the pixel electrode 107 connected to the TFT 106. When a shift clock becomes a high level, the data line selector 104 selects the next data line 102, to which a pixel voltage is applied. In this manner, the data line selector 104 sequentially selects the data line 102 one by one, beginning from the one at the left end, during one horizontal scanning period, so that the next pixel is selected each time a shift clock becomes high, while the signal processing circuit 101 sequentially outputs a pixel voltage to be applied to each pixel.
An increase in the number of pixels and the level of precision for more recent LCDs has resulted in an accompanying increase in the number of pixels to which writing must be performed during one horizontal scanning period. As an example, the number of pixels in the horizontal direction has increased to 1280 in an SXGA (Super Extended Graphics Array) panel, which is twice as many as the 640 horizontal pixels of a VGA (Video Graphics Array) panel. Because the length of one horizontal period does not change as long as the number of the vertical lines remains unchanged, the frequency of a shift clock increases with an increase in the number of pixels, which in turn shortens the time available for voltage application for each pixel. When the number of vertical lines also increases, the length of one horizontal period itself is shortened. In this regard, however, there is the limit of the operation speed for the signal processing circuit 101 and of the response speed of the liquid crystal.
In view of the above problem, a control method has been proposed in which a video signal for one row is allotted to a plurality of phases such that a voltage is applied to a plurality of pixel electrodes in parallel. A control method in which a video signal is allotted to two phases will be described as an example of such a method.
FIG. 2 conceptually depicts an overall structure of an LCD in which a video signal is allotted in two phases. The structure of an LCD drive circuit of FIG. 2 differs from the structure shown in FIG. 1 in that it comprises a multiplexer 121 and a two-stage digital to analog converter (D/A) 122 and is so constructed that a data line selector 123 selects two data lines at the same time.
A video signal externally applied is allotted to either of two phases for each pixel by the multiplexer 121 before being input to the two-stage D/A 122. The two-stage D/A 122 processes data for two pixels simultaneously and outputs pixel voltages for the two pixels. The date line selector 123 selects two adjacent TFTs 109 simultaneously and turns two adjacent data lines into an active state, to which a pixel voltage is simultaneously applied. For example, the data line selector 123 first selects the data lines 102 at the first and second columns. The two-stage D/A 122 outputs pixel voltages according to data to be displayed on the pixels at the first and second columns, and the pixel voltages are applied, via the TFTs, to the pixel electrodes at the first and second columns. After elapse of two shift clock periods, the data line selector 123 then selects the data lines at the third and fourth columns and the two-stage D/A 122 outputs pixel voltages for the pixels at the third and fourth columns. Thereafter, voltage application for two pixels is repeated in the similar manner. Thus, by controlling voltage application such that the pixel voltages are simultaneously applied to a plurality of pixel electrodes, a pixel voltage can be continuously applied over a plurality of shift clock periods so as to secure sufficient time for pixel voltage application in spite of the increase in the number of pixels.
Another control method has been also proposed for driving an LCD in such a manner that a display area is divided in the horizontal direction, as shown in FIG. 3B, such that a voltage is applied to a plurality of pixels in parallel. A method for driving an LCD in a manner that a display area is divided into two regions in the horizontal direction will be described, as an example.
FIG. 3A is a block diagram depicting a section of a drive circuit for driving an LCD in such a manner that the display area is divided into two regions in the horizontal direction. The shown circuit comprises a mutiplexer 131, a memory portion 132, and a two-stage D/A 133, and differs from the structure of FIG. 1 in that it is constructed such that a data line selector 135 simultaneously selects two data lines, as shown in FIG. 3B.
An externally applied video signal for one row is input to the multiplexer 131, which then outputs the earlier half of the input video data, being data corresponding to the left half of the screen, to the memory portion 132. The memory portion 132 temporarily stores the earlier data to output it in synchronism with the latter half of the data, being the data corresponding to the right half of the screen, to the two-stage D/A 133. The two-stage D/A 133 outputs pixel voltages V1 and V2 based on the earlier and latter halves of the data, respectively.
The data line selector 135 simultaneously selects two of the data lines 135, to both of which is simultaneously applied a pixel voltage. For example, the data line selector 135 first selects the data line at the first column and the first data line in the right half of the screen, which is the data line 135A at the 401st column in an LCD having 800 pixels in the horizontal direction, for example. The two-stage driver 133 outputs pixel voltages according to data to be displayed in the pixels at the first and 401st columns, and the pixel voltages are applied, via the TFTs, to the pixel electrodes at the respective columns. The data line selector 135 then selects the data lines at the second and 402nd columns and the two-stage driver 133 outputs pixel voltages for the pixels at these columns. Thereafter, voltage application for two pixels is repeated in the similar manner. This control method also enables voltage application to be controlled such that a voltage is simultaneously applied to a plurality of pixel electrodes. Therefore, it is possible to continuously apply a pixel voltage over a plurality of shift clock periods so as to secure sufficient time for pixel voltage application despite an increase in the number of pixels.
Thus, by allotting a video signal among a plurality of phases such that a pixel voltage is simultaneously applied to a plurality of pixels, the time for applying the pixel voltage can be secured even when the number of pixel is increased.
Different control circuits are presently manufactured corresponding to each of the various types of driving methods and display devices having different number of pixels as described above. However, each type of control circuit which thus varies depending on the driving method or the number of pixels can be manufactured only in a small amount. This disadvantageously increases the manufacturing cost of each circuit.